A bonding wire electrically connects between a semiconductor chip and an outer electrode in a conventional semiconductor device as a surface-mount device disclosed in Japanese Patent Publication (Kokai) No. 2006-278520. The semiconductor device using wire-bonding is simply shown in FIG. 39, for example, and is explained below.
A semiconductor device 1000 includes a semiconductor chip 1001 having a surface electrode 1001a and a back surface electrode 1001b on the front surface and the back surface, respectively. An outer electrode 1002 is connected to the back surface electrode 1001b of the semiconductor chip 1001 via a conductive material (not shown) and the surface electrode 1001a of the semiconductor chip 1001 is connected to an outer electrode 1003 by a bonding wire 1004. The semiconductor device 1000 is encapsulated to be airproofed by an encapsulation resin 1005. In the semiconductor device 1000, wiring pads 1007 configured on a substrate 1006 are mutually connected via the outer electrodes 1002 and 1003 and a conductive material (not shown).
Further, as a feature of other small-type electronic device, for example, a type as shown in FIG. 40 can be listed. A semiconductor device 1010 is constituted with a stacked capacitor 1011 and a pair of outer electrode 1012 connected to the both ends of the stacked capacitor 1011, respectively. A semiconductor chip (not shown) is disposed in the stacked capacitor 1011. Five surfaces of the outer electrode 1012 other than the surface connected to the stacked capacitor 1011 act as an electrode. Furthermore, the outer electrode 1012 is disposed on wiring pads 1014 configured on a substrate 1013. As shown in FIG. 40, a solder 1015 is disposed on the wiring pads 1014 and the outer electrode 1012. The substrate 1013 and the semiconductor device 1010 are electrically connected by the solder 1015.
However, the semiconductor device using the bonding wire disclosed in Japanese Patent Publication (Kokai) No. 2006-278520 has problems mentioned below.
Improvement of electrical characteristics of electron devices, for example, has been desired according to popularization of a cell phone or electronics. An electrical resistance of a bonding wire is increased in the semiconductor device by using the bonding wire. Therefore, improvement in electric characteristics is difficult. Furthermore, as shown in FIG. 39, the surface electrode 1001a of the semiconductor chip 1001 is individually connected to the outer electrode 1003. Consequently, decrease of steps in a fabrication process and shortage of takt time cannot be performed so that productivity cannot be improved.
As shown in FIG. 40, the semiconductor device has a structure that the semiconductor chip is encapsulated in the stacked capacitor. The structure can be improved in electric characteristics due to non-bonding wire as compared to the semiconductor device 1000 having the bonding wire. On the other hand, a problem may occur when the semiconductor chip is encapsulated. The problem is that the semiconductor element in the semiconductor device is failed. The stacked capacitor 1011 is laminated with hard insulators sandwiching as shown in FIG. 40 and is fabricated by thermocompression. When encapsulating the semiconductor chip, a load to the semiconductor chip in thermocompression may provide damages to the semiconductor chip, which leads to degradation of yield in the fabrication process.
Furthermore, peeling between the semiconductor chip and the material sandwiching the semiconductor chip at a contacting interface may be generated in reliability test or a shock accompanying with falling, which may lead to degradation of yield in the fabrication process.
Moreover, display of polarity is necessary for the semiconductor device as shown in both FIG. 39 and FIG. 40. On the other hand, the display of polarity on each semiconductor device generates an obstacle in improvement of productivity.
A method for fabricating the semiconductor device includes disposing the semiconductor chip or the individuated semiconductor element on an electrode or a resin substrate using a mounting tool in the processing steps. The processing steps flows accompanying with absorbing the semiconductor chip or the semiconductor element, picking up, transferring, disposing, absorbing off and absorbing next semiconductor chip or semiconductor element or the like to consume long time. In the processing steps, accuracy of the disposing position on the semiconductor chip or the semiconductor element depends on accuracy of the mounting tool. Accordingly, accuracy improvement of the disposing position has a limitation in the processing steps.